`define DELAY(N, clk) begin \
	repeat(N) @(posedge clk);\
	#1ps;\
end

module testbench();

//-------------------------------------{{{common cfg
timeunit 1ns;
timeprecision 1ps;
initial $timeformat(-9,3,"ns",6);

string tc_name;
int tc_seed;

initial begin
    if(!$value$plusargs("tc_name=%s", tc_name)) $error("no tc_name!");
    else $display("tc name = %0s", tc_name);
    if(!$value$plusargs("ntb_random_seed=%0d", tc_seed)) $error("no tc_seed");
    else $display("tc seed = %0d", tc_seed);
end
//-------------------------------------}}}

//-------------------------------------{{{parameter declare
//-------------------------------------}}}

//-------------------------------------{{{signal declare
logic  cpuif_mode;
logic  cpuif_port_sel;
logic  spt_cpuif_head_err;
logic  spt_cpuif_tail_err;
logic  spt_cpuif_short_pkt;
logic  spt_cpuif_long_pkt;
logic  spt_cpuif_ok_pkt;
logic  core_spt_cs_n;
logic  core_spt_we_n;
logic [9:0] core_spt_addr;
logic [23:0] spt_core_rdata;
logic [23:0] core_spt_wdata;
logic  core_spt_wdata_oe_n;
logic  vid_in;
logic [15:0] data_in;
logic  vid_out;
logic [15:0] data_out;
logic  SRAM_CS_A_N;
logic  SRAM_WE_A_N;
logic [9:0] SRAM_ADDR_A;
logic [23:0] SRAM_RDATA_A;
logic [23:0] SRAM_WDATA_A;
logic  SRAM_WDATA_OEA_N;
logic  SRAM_CS_B_N;
logic  SRAM_WE_B_N;
logic [9:0] SRAM_ADDR_B;
logic [23:0] SRAM_RDATA_B;
logic [23:0] SRAM_WDATA_B;
logic  SRAM_WDATA_OEB_N;
//-------------------------------------}}}

//-------------------------------------{{{clk/rst cfg
logic clk, rst_n;
initial forever #5ns clk = ~clk;
initial begin
    rst_n = 1'b0;
	`DELAY(30, clk);
	rst_n = 1'b1;
end
initial begin
    #100000ns $finish;
end
//-------------------------------------}}}

//-------------------------------------{{{valid sig assign
//-------------------------------------}}}

//-------------------------------------{{{ready sig assign
//-------------------------------------}}}

//-------------------------------------{{{data  sig assign
//-------------------------------------}}}

//-------------------------------------{{{other sig assign
initial begin
    cpuif_mode = $urandom;
    cpuif_port_sel = $urandom;
    core_spt_cs_n = $urandom;
    core_spt_we_n = $urandom;
    core_spt_addr = $urandom;
    core_spt_wdata = $urandom;
    core_spt_wdata_oe_n = $urandom;
    vid_in = $urandom;
    data_in = $urandom;
    SRAM_RDATA_A = $urandom;
    SRAM_RDATA_B = $urandom;
    `DELAY(50, clk);
end

//-------------------------------------}}}

//-------------------------------------{{{rtl inst
spt u_spt(
    .clk_100m(clk),
    .rst_spt_n(rst_n),
    .cpuif_mode(cpuif_mode),
    .cpuif_port_sel(cpuif_port_sel),
    .spt_cpuif_head_err(spt_cpuif_head_err),
    .spt_cpuif_tail_err(spt_cpuif_tail_err),
    .spt_cpuif_short_pkt(spt_cpuif_short_pkt),
    .spt_cpuif_long_pkt(spt_cpuif_long_pkt),
    .spt_cpuif_ok_pkt(spt_cpuif_ok_pkt),
    .core_spt_cs_n(core_spt_cs_n),
    .core_spt_we_n(core_spt_we_n),
    .core_spt_addr(core_spt_addr),
    .spt_core_rdata(spt_core_rdata),
    .core_spt_wdata(core_spt_wdata),
    .core_spt_wdata_oe_n(core_spt_wdata_oe_n),
    .vid_in(vid_in),
    .data_in(data_in),
    .vid_out(vid_out),
    .data_out(data_out),
    .SRAM_CS_A_N(SRAM_CS_A_N),
    .SRAM_WE_A_N(SRAM_WE_A_N),
    .SRAM_ADDR_A(SRAM_ADDR_A),
    .SRAM_RDATA_A(SRAM_RDATA_A),
    .SRAM_WDATA_A(SRAM_WDATA_A),
    .SRAM_WDATA_OEA_N(SRAM_WDATA_OEA_N),
    .SRAM_CS_B_N(SRAM_CS_B_N),
    .SRAM_WE_B_N(SRAM_WE_B_N),
    .SRAM_ADDR_B(SRAM_ADDR_B),
    .SRAM_RDATA_B(SRAM_RDATA_B),
    .SRAM_WDATA_B(SRAM_WDATA_B),
    .SRAM_WDATA_OEB_N(SRAM_WDATA_OEB_N)
);
//-------------------------------------}}}

endmodule
